The present invention relates to a gradation corrector used in correcting the gradation of a video signal in a television receiver, a video tape recorder, a video camera, a video disk or the like.
In recent years, great importance has been attached to gradation correctors in order to provide more clearer images which are required with the increase in size of color television receivers and the improvement in image quality thereof, and more especially, in order to expand the dynamic range of an image on a CRT by passing a video signal through a non-linear amplifier to correct the gradation of the video signal. A U.S. patent application Ser. No. 838,844 entitled "Gradation corrector" was filed on Feb. 21, 1992 (on basis of Japanese patent application No. 3-32794 filed on Feb. 2, 1991). A U.S. patent application Ser. No. 846,143 entitled "Video signal gradation corrector" was filed on Mar. 5, 1992 (on basis of Japanese patent application No. 3-58657 filed on Mar. 22, 1991). A new U.S. patent application entitled "Video signal gradation corrector" is filed on basis of Japanese patent application Nos. 3-123647 and 3-123468 filed on May 28, 1991. These three patent application have been assigned to the same assignee with the present application.
An explanation will be given of a gradation corrector proposed precedently to the present application.
FIG. 3 is a block diagram of the preceding gradation corrector. In FIG. 3, reference numeral 1 designates a black detection circuit for detecting a signal corresponding to a black portion in an input luminance signal to output a black detection signal. Numeral 2 designates a gain control circuit for gain-controlling the black detection signal in accordance with a gain control signal to output an amplified black detection signal. Numeral 3 designates an adder for adding the input luminance signal to the amplified luminance signal to output an output luminance signal. Numeral 4 designates a black peak-hold circuit for holding the black peak level of the output luminance signal to output the voltage with the level as a black peak hold voltage. Numeral 5 designates a comparator for comparing the black peak-hold voltage with a reference voltage. Numeral 6 designates a voltage source for generating the reference voltage.
The operation of the gradation corrector thus constructed will be explained with reference to FIG. 4. FIG. 4 shows waveforms of signals at several points of the gradation corrector of FIG. 3.
First, an input luminance signal a is inputted to the black detection circuit which extracts the black signal corresponding to the portion lower than a predetermined value of the luminance signal to be outputted as a black detection signal b. The black detection signal b is inputted to the gain control circuit 2 which controls its gain in accordance with a gain control voltage f to output an amplified black detection signal c. The signal c is inputted to the adder 3 which adds it to the input luminance signal a to output an output luminance signal d with an extended dynamic range on the black side. The signal d is outputted externally and also inputted to the black peak-hold circuit 4. The peak-hold circuit 4 detects the highest black luminance signal level to output the voltage with the level as a black peak-hold voltage e. The comparator 5 compares the peak-hold voltage e with a reference voltage r generated by the voltage source 6 to feed back a difference between them as a gain control voltage f to the gain control circuit 2. This feed-back system is stabilized when the black peak voltage e becomes equal to the reference voltage g. In this way, when there is a black-detection component, if the corresponding peak voltage is controlled to always be equal to the reference voltage, the dynamic range is extended on the black side to provide gradation correction.
FIG. 5 is a block diagram of another precedent gradation corrector. Reference numeral 7 designates an A/D converter for converting an input luminance signal into a digital value. Numeral 8 designates a histogram memory for obtaining a luminance histogram of the input luminance signal. In general, the luminance level enters an address of the memory 2 and the frequency enters as the data thereof. Numeral 9 designates a histogram accumulation circuit for accumulating the output signals from the histogram memory 8. Numeral 10 designates a cumulative histogram memory for storing therein the result of accumulation by the histogram accumulation circuit 9. In general, the luminance level enters an address of the memory 9 and the frequency enters as data thereof. Numeral 11 designates a look-up table operating circuit which normalizes the respective data from the cumulative histogram memory 10 so that the maximum value resulting from accumulation becomes the maximum value of the output luminance signal. Numeral 12 designates a look-up table memory for storing therein the output signal normalized by the look-up table operating circuit 11. In general, the input luminance level enters an address of the memory 12 and the frequency enters as the data thereof. Numeral 13 designates a D/A converter which converts an output luminance signal in digital value corrected by the look-up table memory 12 into an analog signal. Numeral 14 designates a timing control circuit 14 which makes sequencing of various operations and control for the memories.
The operation of the gradation corrector circuit thus constructed will be explained below. FIG. 6 shows the manner of conversion in the circuit.
First, an input luminance signal a is inputted to the A/D converter 7 which converts it into a digital value to be outputted as a converted input luminance signal h. The histogram memory 8 takes the converted input luminance signal h as an address and adds 1 to the data at the address for each access. By performing this operation during one vertical scanning period, it is possible to detect a histogram distribution of the input luminance signal a. The histogram distribution is shown in FIG. 6(A). The contents of the histogram memory 8 are cleared at every predetermined period to make all the data zero. Usually, this period is set for one vertical scanning period or its integer-times.
Next, data of the histogram memory 8 are read sequentially from the address of 0 by the histogram accumulation circuit 9 which in turn the output signals i. The accumulation result j is stored in the cumulative histogram memory 10. It is shown in FIG. 6(B).
The look-up table operating circuit 11 determines a normalization coefficient so that the maximum value of the cumulative histogram memory 10 is the maximum output luminance level. The look-up table operating circuit 11 performs a normalization operation on all the data in the cumulative histogram memory 10 by use of the determined normalization coefficient. The operation result is stored in the look-up table memory 12. It is shown in FIG. 6(C).
Data in the look-up table memory 12 is read with a converted input luminance signal h as an address and the read data is outputted as a corrected output luminance signal as a corrected output luminance signal m. FIG. 6(D) shows a histogram of the corrected luminance signal m. The D/A converter converts the corrected output luminance signal m into an analog signal d to be outputted.
The timing control circuit 14 controls the operations of various circuits so that the respective parts are performed in the order as described above.
The above precedent correctors have the following defects. The first corrector has a problem that since only a black signal is subjected to gradation correction, a high luminance level signal or an intermediate luminance level signal is not gradation-corrected, and so the dynamic range cannot be improved sufficiently.
The second corrector which is directed to "histogram flattening processing" can extend the dynamic range to 100%. But a normal video signal when subjected to such processing results in quite unlike an actual image.